1. Field of the Invention
The present invention relates in general to a phase locked loop (referred to hereinafter as PLL) circuit, and more particularly to a PLL circuit having a lock holder.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional PLL circuit. As shown in this drawing, the conventional PLL circuit comprises a reference counter 1 for reducing a frequency of a reference signal Ref at a first desired ratio, a programmable counter 2 for reducing a frequency of a voltage controlled oscillating signal VCO at a second desired ratio, and a phase detector 3 for detecting a phase and a frequency of an output signal from the reference counter 1 and a phase and a frequency of an output signal from the programmable counter 2 and outputting error data to an external low pass filter and a lock signal to a lock detector 4 in accordance with the detected result. The lock detector 4 is adapted to input the lock signal from the phase detector 3 and output the inputted lock signal to an external switch.
The operation of the conventional PLL circuit with the above-mentioned construction will hereinafter be described.
First, the reference counter 1 reduces the frequency of the reference signal Ref at the first desired ratio and applies the resultant signal to one input terminal of the phase detector 3. The programmable counter 2 reduces the frequency of the voltage controlled oscillating signal VCO from an external voltage controlled oscillator at the second desired ratio and applies the resultant signal to the other input terminal of the phase detector 3. Then, the phase detector 3 detects whether the phase and the frequency of the output signal from the reference counter 1 are the same as those of the output signal from the programmable counter 2. Upon detecting that the phase and the frequency of the output signal from the reference counter 1 are not the same as those of the output signal from the programmable counter 2, the phase detector 3 outputs a high or low level pulse to the external low pass filter (not shown). Also in this case, the phase detector 3 outputs no lock signal to the lock detector 4.
In detail, when the phase and the frequency of the output signal from the reference counter 1 are greater than those of the output signal from the programmable counter 2, the phase detector 3 outputs the high level pulse to the external low pass filter and no lock signal to the lock detector 4.
In this case, the low pass filter converts the high level pulse from the phase detector 3 into a direct current (DC) value. Then, the low pass filter increases the DC value to increase the frequency of the voltage controlled oscillating signal VCO of the voltage controlled oscillator.
Thereafter, the above operation is repeatedly performed on the basis of the voltage controlled oscillating signal VCO with the increased frequency and the reference signal Ref.
On the contrary, when the phase and the frequency of the output signal from the reference counter 1 are smaller than those of the output signal from the programmable counter 2, the phase detector 3 outputs the low level pulse to the external low pass filter and no lock signal to the lock detector 4.
In this case, the low pass filter converts the low level pulse from the phase detector 3 into a DC value. Then, the low pass filter reduces the DC value to reduce the frequency of the voltage controlled oscillating signal VCO of the voltage controlled oscillator.
Thereafter, the above operation is repeatedly performed on the basis of the voltage controlled oscillating signal VCO with the reduced frequency and the reference signal Ref.
With the above operation repeatedly performed, the phase and the frequency of the output signal from the reference counter 1 become ultimately the same as those of the output signal from the programmable counter 2.
In this case, the phase detector 3 outputs no pulse to the external low pass filter and the lock signal to the lock detector 4.
The lock detector 4 includes a plurality of flip-flops. Upon inputting the lock signal from the phase detector 3, the lock detector 4 detects whether a variation of the inputted lock signal is present for a predetermined time period from the moment that the lock signal is inputted. If it is detected that the variation of the inputted lock signal is not present for the predetermined time period, the lock detector 4 outputs the lock signal to the external switch (not shown).
However, the above-mentioned conventional PLL circuit performs only a function of indicating a locked state. Also, the conventional PLL circuit releases the locked state upon generation of a noise. Further, the conventional PLL circuit requires much current consumption amount because the phase detector, the low pass filter and the voltage controlled oscillator constituting a PLL are operated to hold the locked state continuously.